The present invention generally relates to integrated circuits, and more particularly to testing the integrity of deep trench isolation structures.
Embedded dynamic random access memory (eDRAM) is a critical part of modern semiconductor technologies. This memory may require about one third the space of static random access memory (SRAM) because each bit only requires one transistor that accesses a capacitor. There exist multiple techniques by which to implement a capacitor in an eDRAM device. One way to build the capacitor may be to etch a deep trench in a semiconductor-on-insulator (SOI) substrate and then fill the deep trench with a node dielectric and an inner electrode. The structure may be known as a deep trench capacitor. In such a structure, a layer of conductive material below the buried dielectric layer of the SOI substrate forms a buried plate of the capacitor. The buried plate may also be referred to as a cathode, and may generally be doped silicon. The inner electrode formed within the deep trench is the top plate or anode of the capacitor. The buried plate and the top plate may generally be separated by the node dielectric.
The buried plate, or cathode, for all deep trench capacitors formed in a single SOI substrate may be electrically connected unless otherwise intentionally isolated. One method by which to isolate the buried plate of one deep trench capacitor from the buried plate of another deep trench capacitor may be to create an isolation device extending from a top surface of the SOI substrate to below the buried plate. In some cases the isolation device may completely surround one or more deep trench capacitors separating them from the rest of the chip. Such an isolation device may commonly be referred to as a deep trench moat (DTMoat).
It may be advantageous to test the integrity of the isolation device to ensure the reliability of the semiconductors devices relying on its electrical isolation properties.